DS3232MZ+【PDF 10/23 页】IC RTC W/SRAM I2C 8SOIC

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Sheet目录1994

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DS3232M

±5ppm, I2C Real-Time Clock with SRAM

Maxim Integrated

Aging Offset Register (10h)

Temperature Registers (11h–12h)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SIGN

DATA

The Aging Offset register takes a user-provided value to add to or subtract from the factory-trimmed value that adjusts the

accuracy of the time base. Use of the Aging Offset register is not needed to achieve the accuracy as defined in the Electrical

Characteristics tables.

The Aging Offset code is encoded in two’s complement, with bit 7 representing the SIGN bit. One LSB typically represents a

0.12ppm change in frequency. The change in ppm per LSB is the same over the operating temperature range. Positive offsets

slow the time base and negative offsets quicken the time base.

Temperature Register (Upper Byte = 11h)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

SIGN

DATA

Temperature Register (Lower Byte = 12h)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DATA

Temperature is represented as a 10-bit code with a resolution of 0.25°C and is accessible at location 11h and 12h. The tem-

perature is encoded in two’s complement format. The upper 8 bits, the integer portion, are at location 11h and the lower 2 bits,

the fractional portion, are at location 12h. For example, 00011001 01b = +25.25°C. Upon power reset, the registers are set to

a default temperature of 0°C and the controller starts a temperature conversion. The temperature is read upon initial applica-

tion of VCC or I2C access on VBAT and once every second afterwards with VCC power or once every 10s with VBAT power. The

Temperature registers are also updated after each user-initiated conversion and are read only.

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